Vertical conduction devices in which on state conduction is through an accumulated channel region are well known. U.S. Pat. No. 6,580,123 dated Jun. 17, 2003 in the name of Naresh Thapar (IR-1799) and assigned to the assignee of the present invention shows such a device.
FIG. 1 shows two adjacent cells of such a prior device in cross-section. The device of FIG. 1 comprises an N+ substrate 10 which has an N− epitaxially deposited drift region 10a and base region 11. A high concentration source region diffusion 12 is formed on the top of epitaxial region 11. The side walls of each of trenches 13 are lined with a gate oxide 14, a bottom oxide TBO 15, and top isolation oxide tox, iso 16. A top source contact 20 contacts N+ source region 12 and a bottom drain contact 21 contacts the bottom of N+ substrate 10. Conductive P type polysilicon gates 30 fill the oxide lined trenches 13.
On state conduction in the device of FIG. 1 takes place through the accumulated channel region along the silicon mesa walls within N− channel region 11 which are lined with the gate oxide 14. The device is turned off by shorting the P type gates 30 to the source contact, which depletes out the N− channel region 11. Further, during blocking most of the charge in the N− drift region 10a is coupled to the gate so that Coss is almost identical to Crss.
This type device has several benefits. For example, it has a zero Qrr since there is no body diode, as in a conventional vertical conduction MOSFET. Further, it can have a lower RA, using a sub micron cell pitch. The device can be manufactured with a 4 mask process with no critical alignments. Further, the device has bidirectional capability.
In order to block voltage, the device needs the P type gate 30 with a base resistivity for N− base 11 of about 5 ohm-cm resistivity or higher. Sub-micron mesa widths (the distance between adjacent trenches 14) are needed to obtain complete depletion of the N− channels 11 during turn-off.
As a result of this structure, the threshold voltage Vth is, theoretically about 780 mV and is independent of gate oxide thickness for gate oxide 14.
A limitation found with the above structure is “snap-back” in the BVDSS characteristics. This snap back was observed between 8 to 22 volts, depending on the thickness of region 11. It is believed that this snap-back occurs because thermally or avalanche generated holes are back-injected into the source, leading to the injection of electrons from the source 20 into the N− drift region 10a. 